Experiment 5 – Counters and Timers
I. ABSTRACT
This experiment deals with writing a vhdl code for a 60 second timer applying principles in building counters with sequential codes as well as incorporating other functions namely set, reset, pause, count up and count down.
II. OBJECTIVES
5.1. Create an up-down counter with the following features: Count-up, Count-down, Reset, Pause, Set.
5.2. Create a 60 second count-down timer that would be able to count down 59-0.
III. THEORETICAL FRAMEWORK
A timer is a specialized type of clock. A timer can be used to control the sequence of an event or process.Whereas a stopwatch counts upwards from zero for measuring elapsed time, a timer counts down from a specified time interval, like an hourglass. Timers can be mechanical,electromechanical, electronic (quartz), or even software as all modern computers include digital timers of one kind or another. When the set period expires some timers simply indicate so (e.g., by an audible signal), while others operate electrical switches.
IV. CONCEPTUAL FRAMEWORK
5.1
clock div
Counter
Counter Vector Waveform
Second Counter
Second Counter Vector Waveform
5.2
Clock Div
Counter
Counter Vector Waveform
Second Counter
Second Counter Vector Waveform
Decoder
Circuit Diagram
VI. DATA AND RESULTS
Counter Code (both 5.1 and 5.2)
Library ieee;
Use ieee.std_logic_1164.all;
Entity counter Is
port( clk :in bit;
clr :in bit;
set :in bit;
pause :in bit;
up_down :in bit;
b :in bit;
qin :in integer range 0 to 10;
qout :out integer range 0 to 10);
End counter;
Architecture a Of counter Is
begin
process(clk)
variable cnt :integer range 0 to 10;
begin
if (clk'event and clk='1') then
if (pause='0') then ---pause the clock
cnt:=cnt;
elsif (up_down='1') then
cnt:=cnt+x;
if (cnt>9) then
cnt:=0;
b='1';
end if;
elsif (x=-1) then
cnt:=cnt+x;
if (cnt>9) then
cnt:=9;
b='1';
end if;
end if;
if (set='0') then ---set the counter
cnt:=qin;
end if;
if (clr='0') then ---reset the counter
cnt:=0;
end if;
end if;
qout<=cnt;
end process;
end a;
Second Counter Code (both 5.1 and 5.2)
Library ieee;
Use ieee.std_logic_1164.all;
Entity second_counter Is
port( clk :in bit;
clr :in bit;
set :in bit;
pause :in bit;
up_down :in bit;
qin :in integer range 0 to 10;
qout :out integer range 0 to 10 );
End second_counter;
Architecture a Of second_counter Is
begin
process(clk)
variable cnt :integer range 0 to 10;
variable x :integer;
begin
if (up_down='1') then
x:=1;
else
x:=-1;
end if;
if (clk'event and clk='1') then
if (pause='0') then
cnt:=cnt;
elsif (x=1) then
cnt:=cnt+x;
if (cnt>5) then ---starts counting 0 to 5;
cnt:=0;
end if;
elsif (x=-1) then
cnt:=cnt+x;
if (cnt>5) then ---starts counting 5 to 0;
cnt:=5;
end if;
end if;
if (clr='0') then
cnt:=0;
end if;
if (set='0') then
cnt:=qin;
end if;
end if;
qout<=cnt;
end process;
end a;
Decoder Code
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decoder IS
PORT (I : IN BIT_VECTOR(3 DOWNTO 0);
O : OUT BIT_VECTOR(6 DOWNTO 0));
END decoder;
ARCHITECTURE a OF decoder IS
BEGIN
WITH I SELECT
O <="0000001"WHEN"0000",
"1001111"WHEN"0001",
"0010010"WHEN"0010",
"0000110"WHEN"0011",
"1001100"WHEN"0100",
"0100100"WHEN"0101",
"0100000"WHEN"0110",
"0001111"WHEN"0111",
"0000000"WHEN"1000",
"0000100"WHEN"1001",
"0000010"WHEN"1010",
"1100000"WHEN"1011",
"0110001"WHEN"1100",
"1000010"WHEN"1101",
"0010000"WHEN"1110",
"0111000"WHEN"1111";
END a;
5.1
