Experiment 3 - Combinational Logic Circuit of a Multiplexer and a Comparator
I. ABSTRACT
We will be implementing in this experiment, using combinational logic circuits, a comparator and multiplexer. Outputs can only be determined by their current input state.
II. OBJECTIVE
To be able to implement in VHDL the combinational logic circuits of a multiplexer and a comparator.
III. THEORETICAL FRAMEWORK
The outputs of Combinational Logic circuits are only determined by their current input state as they have no feedback, and any changes to the signals being applied to their inputs will immediately have an effect at the output. In other words, in a Combination Logic circuit, if the input condition changes state so too does the output as combinational circuits have No Memory.
They are made up from basic logic AND, OR or NOT gates that are "combined" or connected together to produce more complicated switching circuits. As combination logic circuits are made up from individual logic gates they can also be considered as "decision making circuits" and combinational logic is about combining logic gates together to process two or more signals in order to produce at least one output signal according to the logical function of each logic gate. Common combinational circuits made up from individual logic gates include Multiplexers,Decoders and De-multiplexers, Full and Half Adders etc.
A multiplexer, abbreviated mux, is a device that has multiple inputs and one output.
Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that compare the digital signals at their input terminals and produces an output depending upon the condition of the inputs. For example, whether input A is greater than, smaller than or equal to input B etc. Digital Comparators can compare a variable or unknown number for example A (A1, A2, A3, .... An, etc) against that of a constant or known value such as B (B1, B2, B3, .... Bn, etc) and produce an output depending upon the result.
IV. CONCEPTUAL FRAMEWORK
The schematic symbol for multiplexers is
The truth table for a 2-to-1 multiplexer is
V. DATA AND RESULTS
1) 2-1 muiltiplexer
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY yayi IS
PORT (a,b : IN BIT_VECTOR(3 DOWNTO 0);
x:in bit;
z : OUT BIT_Vector(3 DOWNTO 0));
END yayi;
ARCHITECTURE exx OF yayi IS
BEGIN
z <= a when x ='0' else b;
end exx;
2) comparator
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY maxx IS
PORT (a,b : IN BIT_VECTOR(3 DOWNTO 0);
x : OUT BIT );
END maxx;
ARCHITECTURE yahu OF maxx IS
BEGIN
x <='1' when b > a else '0';
end yahu;
3) 7segment using common anode
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY etonatalaga IS
PORT (I : IN BIT_VECTOR(3 DOWNTO 0);
O : OUT BIT_VECTOR(6 DOWNTO 0));
END etonatalaga;
ARCHITECTURE cutee OF etonatalaga IS
BEGIN
WITH I SELECT
O <="0000001" WHEN "0000",
"1001111"WHEN"0001",
"0010010"WHEN"0010",
"0000110"WHEN"0011",
"1001100"WHEN"0100",
"0100100"WHEN"0101",
"0100000"WHEN"0110",
"0001111"WHEN"0111",
"0000000"WHEN"1000",
"0000100"WHEN"1001",
"0000010"WHEN"1010",
"1100000"WHEN"1011",
"0110001"WHEN"1100",
"1000010"WHEN"1101",
"0010000"WHEN"1110",
"0111000"WHEN"1111";
END cutee;
VI. ANALYSIS
The exercise is composed of 3 different circuit on which has 3 different functions. The first one is the multiplexer where its function has 2 inputs it maybe 0 or 1 that has only one output. The second circuit is the comparator where its function is mainly to compare the inputs bits. In the circuit it chooses the higher bits of the inputs and the last part circuit would be the 7 segment decoder. These where combined to form one new circuit, it’s function is to have a 7 segment decoder that has the ability to compare its input bits. The higher input would be chosen and will not change its value.
VII. CONCLUSION
The circuit done was somewhat exciting and challenging in our part students. Here we have made 3 different circuit and cascaded it into one that may have new function and features. In this type of experiment we learned and proved its application (The VHDL), that project circuit may be design, verified and simulate before applying it into real hardware. Less time and effort may be it advantages and may be effective.
