Experiment 4 – Sequential Code
I. ABSTRACT
This experiment deals with writing a sequential code for an up counter with the required parameters.
II. OBJECTIVES
1. To be able to create a sequential code using VHDL.
1.1. Create an up-counter with an input and reset.
1.2. Create a 2-digit count up counter using count up counter using down module in 1.1 and a BCD decoder.
III. THEORETICAL FRAMEWORK
In digital logic and computing, a counter is
a device which stores (and sometimes displays) the number of times a particular event orprocess has occurred, often in relationship to a
clock signal. In practice, there are two types of counters: Up counters, which increase (increment) in value and Down counters, which decrease (decrement) in value.
In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop, and a wide variety of designs exist, e.g.:
Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-flops
Synchronous counter – all state bits change under control of a single clock
Decade counter – counts through ten states per stage
Up–down counter – counts both up and down, under command of a control input
Ring counter – formed by a shift register with
feedback connection in a ring
Johnson counter – a twisted ring counter
Cascaded counter
Each is useful for different applications. Usually, counter circuits are digital in nature, and count in natural binary. Many types of counter circuit are available as digital building blocks, for example a number of chips in the 4000 series implement different counters.
Occasionally there are advantages to using a counting sequence other than the natural binary sequence—such as the binary coded decimalcounter, a linear feedback shift register counter, or a Gray-code counter. Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.
IV. CONCEPTUAL FRAMEWORK
Counter
Counter Vector Waveform
Decoder
Circuit Diagram
V. DATA AND RESULTS
1.1
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY etonatalaga IS
PORT (I : IN BIT_VECTOR(3 DOWNTO 0);
O : OUT BIT_VECTOR(6 DOWNTO 0));
END etonatalaga;
ARCHITECTURE cutee OF etonatalaga IS
BEGIN
WITH I SELECT
O <="0000001" WHEN "0000",
"1001111"WHEN"0001",
"0010010"WHEN"0010",
"0000110"WHEN"0011",
"1001100"WHEN"0100",
"0100100"WHEN"0101",
"0100000"WHEN"0110",
"0001111"WHEN"0111",
"0000000"WHEN"1000",
"0000100"WHEN"1001",
"0000010"WHEN"1010",
"1100000"WHEN"1011",
"0110001"WHEN"1100",
"1000010"WHEN"1101",
"0010000"WHEN"1110",
"0111000"WHEN"1111";
END cutee;
1.2
Library ieee;
Use ieee.std_logic_1164.all;
Entity pierrecardin is
Port (x, y :in std_logic;
a: out std_logic_vector(0 to 3):="0000";
b: out std_logic);
End pierrecardin;
Architecture counter of pierrecardin is
begin
Process
Variable timer: integer range 0 to 10 :=0;
begin
wait until (x'EVENT AND x = '1');
timer := timer + 1;
If (timer = 10) Then
b <= '1';
timer := 0; else b<='0';
End If;
If (y = '0') then timer:=0;
End If;
case timer is
when 0 => a <= "0000";
when 1 => a <= "0001";
when 2 => a <= "0010";
when 3 => a <= "0011";
when 4 => a <= "0100";
when 5 => a <= "0101";
when 6 => a <= "0110";
when 7 => a <= "0111";
when 8 => a <= "1000";
when 9 => a <= "1001";
when 10 => a <= "0000";
end case;
end process;
end counter;
VI. ANALYSIS
The experiment requires us to make an up-counter with an input and reset. We have successfully created a 2-digit up counter which counts up to 99 before reseting. At any given time, we may also reset the counter back to zero. This particular sequential code works by pushing the assigned button in the DE board for it to count up or reset.
VII. CONCLUSION
We have concluded that in learning to implement sequential data in VHDL, we would be able to easily apply this in a number of hardware devices such as a digital score board or anything that requires counting digitally.
