Experiment 2 – Concurrent Code

I. ABSTRACT

This experiment deals with writing concurrent codes for a 4-bit BCD 7-segment and for an 8-bit multiplexer.

II. OBJECTIVES

1. To be able to implement concurrent data to VHDL.

1.1. VHDL code for 4-bit BCD 7-segment

1.2. VHDL for 8-bit multiplexer

III. THEORETICAL FRAMEWORK

A seven segment display, as its name indicates, is composed of seven elements. Individually on or off, they can be combined to produce simplified representations of the Arabic numerals. Often the seven segments are arranged in an oblique (slanted) arrangement, which aids readability. In most applications, the seven segments are of nearly uniform shape and size (usually elongated hexagons, though trapezoids and rectangles can also be used), though in the case of adding machines, the vertical segments are longer and more oddly shaped at the ends in an effort to further enhance readability.

A multiplexer or mux (occasionally the terms muldex or muldem are also found for a combination multiplexer-demultiplexer) is a device that performs multiplexing; it selects one of many analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2ⁿ inputs has n select lines, which are used to select which input line to send to the output.

Concurrent computing is a form of computing in which programs are designed as collections of interacting computational processes that may be executed in parallel. Concurrent programs can be executed sequentially on a single processor by interleaving the execution steps of each computational process, or executed in parallel by assigning each computational process to one of a set of processors that may be close or distributed across a network. The main challenges in designing concurrent programs are ensuring the correct sequencing of the interactions or communications between different computational processes, and coordinating access to resources that are shared among processes. A number of different methods can be used to implement concurrent programs, such as implementing each computational process as an operating system process, or implementing the computational processes as a set of threads within a single operating system process.

IV. CONCEPTUAL FRAMEWORK

Multiplexer Flowchart

V. DATA AND RESULTS

VHDL code for 4-bit BCD 7-segment

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY etonatalaga IS

PORT (I : IN BIT_VECTOR(3 DOWNTO 0);

O : OUT BIT_VECTOR(6 DOWNTO 0));

END etonatalaga;

ARCHITECTURE cutee OF etonatalaga IS

BEGIN

WITH I SELECT

O <="0000001" WHEN "0000",

"1001111"WHEN"0001",

"0010010"WHEN"0010",

"0000110"WHEN"0011",

"1001100"WHEN"0100",

"0100100"WHEN"0101",

"0100000"WHEN"0110",

"0001111"WHEN"0111",

"0000000"WHEN"1000",

"0000100"WHEN"1001",

"0000010"WHEN"1010",

"1100000"WHEN"1011",

"0110001"WHEN"1100",

"1000010"WHEN"1101",

"0010000"WHEN"1110",

"0111000"WHEN"1111";

END cutee;

VHDL for 8-bit multiplexer

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY wiwi IS

PORT (x, y, z, a, b, c, d, e, f, g, h : In bit;

q : OUT BIT);

END wiwi;

ARCHITECTURE lolipop OF wiwi IS

BEGIN

q <= (a AND not x AND not y AND not z) OR

(b AND not x AND not y AND z) OR

(c AND not x AND y AND not z) OR

(d AND not x AND y AND z) OR

(e AND x AND not y AND not z) OR

(f AND x And not y AND z) OR

(g AND x AND y AND not z) OR

(h AND z AND y AND z);

END lolipop;

Video of results

4-bit BCD 7-segment

8-bit multiplexer

VI. ANALYSIS

The first part of the experiment requires us to again simulate a 4-bit BCD 7-segment but this time using concurrent codes. This saved our group significant time and effort compared to the previous laboratory experiment. Once we figured out how to write the VHDL code, it is only a matter of compiling and simulating it on the DE2. The Second part deals with an 8-bit multiplexer. the goal is to incorporate the various inputs into one output which is done with OR and AND gates written in the VHDL code yeilding the desired result on the DE2.

VII. CONCLUSION

We have concluded that in learning to implement concurrent data in VHDL, we would be able to speed up the whole process of simulation be it a 4-bit BCD 7-segment or an 8-bit multiplexer.