Experiment 1 – Introduction to VHDL

I. ABSTRACT

This experiment introduces us to VHDL, particularly Quartus II and some of its basic functions. It is a powerful software that we used to simulate different logic gates.

II. OBJECTIVES

1. To be familiarized with Quartus II for implementing VHDL design and graphical design.

1.1. VHDL code for AND, OR, NAND, NOT gate

1.2. 4-bit BCD for 7-segment

III. THEORETICAL FRAMEWORK

VHDL (VHSIC hardware description language; VHSIC: very-high-speed integrated circuit) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits.

The Altera DE2 development and education board provides an ideal vehicle for learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone II FPGA, the DE2 board offers state-of-the-art technology suitable for univer

sity and college laboratory use, a wide range of design projects, as well as sophisticated digital system development.

The Karnaugh map (K-map for short), Maurice Karnaugh's 1953 refinement of Edward Veitch's 1952 Veitch diagram, is a method to simplify Boolean algebra expressions. The Karnaugh map reduces the need for extensive calculations by taking advantage of humans' pattern-recognition capability, permitting the rapid identification and elimination of potential race conditions.

In a Karnaugh map the boolean variables are transferred (generally from a truth table) and ordered according to the principles of Gray code in which only one variable changes in between squares. Once the table is generated and the output possibilities are transcribed, the data is arranged into the largest possible groups containing 2ⁿ cells (n=0,1,2,3...) and the minterm is generated through the axiom laws of boolean algebra.

IV. CONCEPTUAL FRAMEWORK

Circuit Schematic

V. DATA AND RESULTS

VHDL code for AND, OR, NAND, NOT gate

AND gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY and_gate IS

PORT ( a, b : IN BIT;

x : OUT BIT);

END and_gate;

ARCHITECTURE a OF and_gate IS

BEGIN

x <= a AND b;

END a;

OR gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY or_gate IS

PORT ( a, b : IN BIT;

x : OUT BIT);

END or_gate;

ARCHITECTURE a OF or_gate IS

BEGIN

x <= a OR b;

END a;

NOT gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY not_gate IS

PORT ( a : IN BIT;

x : OUT BIT);

END not_gate;

ARCHITECTURE a OF not_gate IS

BEGIN

x <= NOT a ;

END a;

NAND gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY nand_gate IS

PORT ( a, b : IN BIT;

x : OUT BIT);

END nand_gate;

ARCHITECTURE a OF nand_gate IS

BEGIN

x <= a NAND b;

END a;

Truth Table

4-bit BCD for 7-segment

Videos/Pictures of results

AND gate

OR gate

NAND gate

NOT gate

4-bit BCD for 7-segment

VI. ANALYSIS

This is a two part VHDL familiarization experiment. First we dealt with implementing four logic gates (AND,OR,NOT,NAND) which was quite simple. Second, we implemented a 4-bit BCD 7 segment in which the output is simulated on a DE2. This part took our group quite a while for the process requires us to create a truth table, derive the equations of each required output (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f) by means of K-mapping, draw the equivalent circuit schematic and to finally write the data in Quartus II.

VII. CONCLUSION

We have concluded that having a firm familiarization with Quartus II can allow us to implement various VHDL and graphical designs. This would allow us to save time and effort in implementing said designs on actual hardware. We have also learned to write and simulate the VHDL codes for AND, OR, NOT, NAND gates as well as a 4-bit BCD 7-segment in this first laboratory experiment.