Experiment 2 – Concurrent Code

I. ABSTRACT

This experiment deals with writing concurrent codes for a 4-bit BCD 7-segment and for an 8-bit multiplexer.

II. OBJECTIVES

1. To be able to implement concurrent data to VHDL.

1.1. VHDL code for 4-bit BCD 7-segment

1.2. VHDL for 8-bit multiplexer

III. THEORETICAL FRAMEWORK

A seven segment display, as its name indicates, is composed of seven elements. Individually on or off, they can be combined to produce simplified representations of the Arabic numerals. Often the seven segments are arranged in an oblique (slanted) arrangement, which aids readability. In most applications, the seven segments are of nearly uniform shape and size (usually elongated hexagons, though trapezoids and rectangles can also be used), though in the case of adding machines, the vertical segments are longer and more oddly shaped at the ends in an effort to further enhance readability.

A multiplexer or mux (occasionally the terms muldex or muldem are also found for a combination multiplexer-demultiplexer) is a device that performs multiplexing; it selects one of many analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2ⁿ inputs has n select lines, which are used to select which input line to send to the output.

Concurrent computing is a form of computing in which programs are designed as collections of interacting computational processes that may be executed in parallel. Concurrent programs can be executed sequentially on a single processor by interleaving the execution steps of each computational process, or executed in parallel by assigning each computational process to one of a set of processors that may be close or distributed across a network. The main challenges in designing concurrent programs are ensuring the correct sequencing of the interactions or communications between different computational processes, and coordinating access to resources that are shared among processes. A number of different methods can be used to implement concurrent programs, such as implementing each computational process as an operating system process, or implementing the computational processes as a set of threads within a single operating system process.

IV. CONCEPTUAL FRAMEWORK

Multiplexer Flowchart

V. DATA AND RESULTS

VHDL code for 4-bit BCD 7-segment

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY etonatalaga IS

PORT (I : IN BIT_VECTOR(3 DOWNTO 0);

O : OUT BIT_VECTOR(6 DOWNTO 0));

END etonatalaga;

ARCHITECTURE cutee OF etonatalaga IS

BEGIN

WITH I SELECT

O <="0000001" WHEN "0000",

"1001111"WHEN"0001",

"0010010"WHEN"0010",

"0000110"WHEN"0011",

"1001100"WHEN"0100",

"0100100"WHEN"0101",

"0100000"WHEN"0110",

"0001111"WHEN"0111",

"0000000"WHEN"1000",

"0000100"WHEN"1001",

"0000010"WHEN"1010",

"1100000"WHEN"1011",

"0110001"WHEN"1100",

"1000010"WHEN"1101",

"0010000"WHEN"1110",

"0111000"WHEN"1111";

END cutee;

VHDL for 8-bit multiplexer

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY wiwi IS

PORT (x, y, z, a, b, c, d, e, f, g, h : In bit;

q : OUT BIT);

END wiwi;

ARCHITECTURE lolipop OF wiwi IS

BEGIN

q <= (a AND not x AND not y AND not z) OR

(b AND not x AND not y AND z) OR

(c AND not x AND y AND not z) OR

(d AND not x AND y AND z) OR

(e AND x AND not y AND not z) OR

(f AND x And not y AND z) OR

(g AND x AND y AND not z) OR

(h AND z AND y AND z);

END lolipop;

Video of results

4-bit BCD 7-segment

8-bit multiplexer

VI. ANALYSIS

The first part of the experiment requires us to again simulate a 4-bit BCD 7-segment but this time using concurrent codes. This saved our group significant time and effort compared to the previous laboratory experiment. Once we figured out how to write the VHDL code, it is only a matter of compiling and simulating it on the DE2. The Second part deals with an 8-bit multiplexer. the goal is to incorporate the various inputs into one output which is done with OR and AND gates written in the VHDL code yeilding the desired result on the DE2.

VII. CONCLUSION

We have concluded that in learning to implement concurrent data in VHDL, we would be able to speed up the whole process of simulation be it a 4-bit BCD 7-segment or an 8-bit multiplexer.

Experiment 1 – Introduction to VHDL

I. ABSTRACT

This experiment introduces us to VHDL, particularly Quartus II and some of its basic functions. It is a powerful software that we used to simulate different logic gates.

II. OBJECTIVES

1. To be familiarized with Quartus II for implementing VHDL design and graphical design.

1.1. VHDL code for AND, OR, NAND, NOT gate

1.2. 4-bit BCD for 7-segment

III. THEORETICAL FRAMEWORK

VHDL (VHSIC hardware description language; VHSIC: very-high-speed integrated circuit) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.

Quartus II is a software tool produced by Altera for analysis and synthesis of HDL designs, which enables the developer to compile their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer.

A logic gate performs a logical operation on one or more logic inputs and produces a single logic output. The logic normally performed is Boolean logic and is most commonly found in digital circuits.

The Altera DE2 development and education board provides an ideal vehicle for learning about digital logic, computer organization, and FPGAs. Featuring an Altera Cyclone II FPGA, the DE2 board offers state-of-the-art technology suitable for univer

sity and college laboratory use, a wide range of design projects, as well as sophisticated digital system development.

The Karnaugh map (K-map for short), Maurice Karnaugh's 1953 refinement of Edward Veitch's 1952 Veitch diagram, is a method to simplify Boolean algebra expressions. The Karnaugh map reduces the need for extensive calculations by taking advantage of humans' pattern-recognition capability, permitting the rapid identification and elimination of potential race conditions.

In a Karnaugh map the boolean variables are transferred (generally from a truth table) and ordered according to the principles of Gray code in which only one variable changes in between squares. Once the table is generated and the output possibilities are transcribed, the data is arranged into the largest possible groups containing 2ⁿ cells (n=0,1,2,3...) and the minterm is generated through the axiom laws of boolean algebra.

IV. CONCEPTUAL FRAMEWORK

Circuit Schematic

V. DATA AND RESULTS

VHDL code for AND, OR, NAND, NOT gate

AND gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY and_gate IS

PORT ( a, b : IN BIT;

x : OUT BIT);

END and_gate;

ARCHITECTURE a OF and_gate IS

BEGIN

x <= a AND b;

END a;

OR gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY or_gate IS

PORT ( a, b : IN BIT;

x : OUT BIT);

END or_gate;

ARCHITECTURE a OF or_gate IS

BEGIN

x <= a OR b;

END a;

NOT gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY not_gate IS

PORT ( a : IN BIT;

x : OUT BIT);

END not_gate;

ARCHITECTURE a OF not_gate IS

BEGIN

x <= NOT a ;

END a;

NAND gate:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY nand_gate IS

PORT ( a, b : IN BIT;

x : OUT BIT);

END nand_gate;

ARCHITECTURE a OF nand_gate IS

BEGIN

x <= a NAND b;

END a;

Truth Table

4-bit BCD for 7-segment

Videos/Pictures of results

AND gate

OR gate

NAND gate

NOT gate

4-bit BCD for 7-segment

VI. ANALYSIS

This is a two part VHDL familiarization experiment. First we dealt with implementing four logic gates (AND,OR,NOT,NAND) which was quite simple. Second, we implemented a 4-bit BCD 7 segment in which the output is simulated on a DE2. This part took our group quite a while for the process requires us to create a truth table, derive the equations of each required output (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f) by means of K-mapping, draw the equivalent circuit schematic and to finally write the data in Quartus II.

VII. CONCLUSION

We have concluded that having a firm familiarization with Quartus II can allow us to implement various VHDL and graphical designs. This would allow us to save time and effort in implementing said designs on actual hardware. We have also learned to write and simulate the VHDL codes for AND, OR, NOT, NAND gates as well as a 4-bit BCD 7-segment in this first laboratory experiment.